1. Technical Field
The present invention relates to a semiconductor device, and more particularly, to a circuit and method of generating a boosted voltage while maintaining a constant difference between the boosted voltage and an array reference voltage.
2. Discussion of the Related Art
Dynamic random access memories (DRAMs) typically use a boosted voltage that has a higher value than that of an external power voltage to control word lines of memory cells in a memory cell array. An array reference voltage is commonly known as a reference voltage that is applied to the memory cell array and/or a peripheral circuit of the memory cell array.
When a rate of the boosted voltage is changed to be greater than that of the array reference voltage, in a general boosted voltage generating circuit, the boosted voltage rises to a high voltage level when in a test mode and a burn-in stress mode. Accordingly, transistors of the memory cells are required to bear the higher boosted voltage. Further, when applying a voltage stress to a device under test (DUT) at a wanted and/or desired array reference voltage, the DUT should be able to bear the additional stress caused by the higher boosted voltage.
However, as the array reference voltage that is used when applying a voltage stress is set to a lower voltage level than the wanted and/or desired voltage due to the higher boosted voltage, excess time is taken to test the DUT.